1. Field of the Invention
The invention is in the field of integrated circuits ("ICs"), and more particularly, solves a problem posed by the inclusion of electrostatic discharge ("ESD") protection circuits within integrated circuits.
2. Description of the Prior Art
Integrated circuits are susceptible to damage when they are subjected to electrostatic discharge (ESD), more commonly known as "static electricity". While the discharge of static electricity can be a "shocking" experience for humans, the effect is usually fleeting. However, the effect on an IC can be permanent. The energy from the discharge of static electricity can be enough to vaporize conductor paths in an IC, causing the IC to be completely inoperable, to function in an unpredictable way, or to create defects which shorten the life of the IC. ESD events can occur at any time during the life of the part but most events that cause damage occur between the time that the circuit is manufactured in wafer form and the time that the circuit is physically mounted in the circuit board that connects the integrated circuit into the system where it is to be used.
ICs are usually protected from ESD damage by including extra device structures that are designed to absorb the ESD events while not causing an undue effect on the performance of the circuit. These structures can be as simple as a fuse or diode, or more complicated, such as grounded NMOS transistors or bipolar transistors in latchback configuration. For high performance, high frequency applications, the capacitance of the ESD protection circuitry can be the limiting factor on the performance of the circuit.
U.S. Pat. No. 5,731,945 (Bertin et al) discloses a multichip integrated structure in which various IC wafers are bonded together to form a single unitary structure. Conductors on side surfaces of the wafers electrically couple the circuits on adjoining wafers. Bertin discloses how to disconnect redundant circuitry in individual wafers of the bonded pre-encapsulated structure, including redundant ESD protection to reduce the overall capacitive loading. Bertin indicates that in some instances, only one ESD circuit need be coupled in circuit to provide ESD protection for the entire multi-wafer bonded IC structure. Bertin discloses the use of fuses, antifuses, etching techniques, and focused ion beam personalization for ESD customization prior to packaging of the multi-wafer structure. Bertin further discloses the use of active circuitry, such as transistor pass gates, to selectively decouple ESD protection from I/O nodes after an IC has been packaged and installed in a system.
A disadvantage of Bertin's structure is that deselection of ESD circuits by fusing and selective wiring is done after the wafers are bonded to each other, but prior to encapsulation. A disadvantage of Bertins structure with respect to active circuit control is the complication of adding internal control circuitry to activate the switching transistors. Furthermore, the switching transistor, even if selected to be of low capacitance, still burdens the I/O nodes. Additionally, ESD protection and its associated loading are still provided to protect the selection node that provides the selection signal to the ESD selection transistor.